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BJ8P508/153
OTP ROM
BJ8P508/153
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8-BIT MICRO-CONTROLLER
Version 2.0
BJ8P508/153
OTP ROM
Application Note
AN-001 Q & A on ICE53S AN-002 The Set-up Timing and Pin Change Wake-up Function Application
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Internal RC Oscillator Mode
This specification is subject to change without prior notice.
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OTP ROM
1. GENERAL DESCRIPTION
BJ8P508/153 is an 8-bit microprocessor with low-power and high-speed CMOS technology. It is equipped
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with a 1024*13-bits Electrical One Time Programmable Read Only Memory (OTP-ROM) with it. It provides a PROTECTION bit to prevent intrusion of user's code in the OTP memory well as 15 OPTION bits to match user's rquirements. With its OTP-ROM feature, the BJ8P508/153 offers users a convenient way of developing and verifying their programs. Moreover, user developed code can be easily programmed with the EMC writer.
This specification is subject to change without prior notice.
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2. FEATURES
* 8-lead packages : BJ8P508; 14-lead packages:BJ8P153 * Operating voltage range : 2.3V~5.5V
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* Available in temperature range: 0C~70C * Operating frequency range (base on 2 clocks): * Crystal mode: DC~20MHz at 5V, DC~8MHz at 3V, DC~4MHz at 2.3V. * ERC mode: DC~4MHz at 5V, DC~4MHz at 3V, DC~4MHz at 2.3V. * Low power consumption: * less then 1.5 mA at 5V/4MHz * typical of 15 A, at 3V/32KHz * typical of 1A, during the sleep mode * 1024 13 bits on chip ROM * Built-in calibrated IRC oscillators (8MHz, 4MHz, 1MHz, 455KHz ) * Programmable prescaler of oscillator set-up time * One security register to prevent the code in the OTP memory from intruding * One configuration register to match the user's requirements * 32 8 bits on chip registers (SRAM, general purpose register) * 2 bi-directional I/O ports * 5 level stacks for subroutine nesting * 8-bit real time clock/counter (TCC) with selective signal sources and trigger edges, and with overflow interrupt * Power down mode (SLEEP mode) * Three available interruptions * TCC overflow interrupt * Input-port status changed interrupt (wake up from the sleep mode) * External interrupt * Programmable free running watchdog timer * 7 programmable pull-high I/O pins * 7 programmable open-drain I/O pins * 6 programmable pull-down I/O pins * Two clocks per instruction cycle * Package type: 8 pins SOP, PDIP * 8 pin DIP 300mil: BJ8P508APJ
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OTP ROM
* 8 pin SOP 150mil: 8P508ANJ 14 pins SOP, PDIP * 14 pin DIP 300mil: BJ8P153APJ, * 14 pin SOP 150mil: BJ8P153SNJ
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The names in BJX's ERP are BJ8P508APJ,8P508ANJ,BJ8P153APJ/78P153SPJ,BJ8P153SNJ.
* The transient point of system frequency between HXT and LXT is around 400KHz.
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3. PIN ASSIGNMENTS
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FIG1.pin assignments Table 1. pin description Symbol Vdd P65/OSCI Type I/O Function Power supply *General purpose I/O pin. *External clock signal input. *Input pin of XT oscillator. *Pull-high/open-drain *Wake up from sleep mode when the status of the pin changes. *General purpose I/O pin. *External clock signal input. *Input pin of XT oscillator *Pull-high/open-drain *Wake up from sleep mode when the status of the pin changes. *If set as /RESET and remain at logic low,the device will be uder reset. *Wake up from sleep mode when the status of the pin changes. *Voltage on/RESET must not exceed Vdd during the normal mode. *Internal Pull-high is on if defined as /RESET. *P63 is input pin only. *General purpose I/O pin. *Pull-high/open-drain/pull-down. *Wake up from sleep mode when the status of the pin changes. *Schmitt Trigger input during the programming mode. *General purpose I/O pin. *Pull-high/open-drain/pull-down. *Wake up from sleep mode when the status of the pin changes. *Schmitt Trigger input during the programming mode. *General purpose I/O pin. *Pull-high/open-drain/pull-down. *Wake up from sleep mode when the status of the pin changes. *Schmitt Trigger input during the programming mode. *External interrupt pin triggered by falling edge.
P64/OSCO
I/O
P63//RESET
I
P62/TCC
I/O
P61
I/O
P60//INT
I/O
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*General purpose I/O pin. *Pull-high/open-drain *Wake up from sleep mode when the status of the pin changes. *General purpose I/O pin. *Pull-down. *General purpose I/O pin. *Ground.
P66,P67 P50~P53 P53 VSS
I/O I/O I/O -
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4. FUNCTION DESCRIPTION
OSCO OSCI
Oscillator/Timing Prescaler ROM
/RESET
WDT timer
TCC
/INT
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R2
Stack
Built-in OSC
RAM
Interrupt Controller
Instruction Register
R3
ALU
R4
R1(TCC)
Instruction Decoder
ACC
DATA & CONTROL BUS
P60 P61 P62/TCC P63//REST P64/OSCO P65/OSCI P66 P67
IOC6 R6
I/O PORT 6
IOC5 R6
I/O PORT 5
P50 P51 P52 P53
Fig. 2 Functional block diagram
4.1 Operational Registers
1. R0 (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is to be an indirect addressing pointer. Any instruction using R0 as a pointer, actually accesses data pointed by the RAM Select Register (R4).
2. R1 (Time Clock /Counter)
* Increased by an external signal edge, which is defined by TE bit (CONT-4) through the TCC pin, or by the instruction cycle clock. * Writable and readable as any other registers. * Defined by resetting PAB (CONT-3). * The prescaler is assigned to TCC if the PAB bit (CONT-3) is reset. * The contents of the prescaler counter is cleared only when a value is written to TCC register.
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3. R2 (Program Counter) & Stack
* Depending on the device type, R2 and hardware stack are 10-bit wide. The structure is depicted in Fig.3. *102413 bits on-chip OTP ROM addresses to the relative programming instruction
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codes. One program page is 1024 words long. * R2 is set as all "0"s when at RESET condition. * "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to go to any location within a page. * "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page. * "RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top-level stack. * "ADD R2,A" allows the contents of `A' to be added to the current PC, and the ninth and tenth bits of the PC are cleared. * "MOV R2,A" allows to load an address from the "A" register to the lower 8 bits of the PC, and the ninth and tenth bits of the PC are cleared. * Any instruction that is written to R2 (e.g. "ADD R2,A", "MOV R2,A", "BC R2,6",) will cause the ninth and tenth bits (A8,A9) of the PC to be cleared. Thus, the computed jump is limited to the first 256 locations of a page. * All instructions are single instruction cycle (fclk/2 or fclk/4), except for the instruction that would change the contents of R2. This instruction will need one more instruction cycle. PC (A9 ~ A0)
Reset Vector Interrupt Vector
Stack Level 1 Stack Level 2 Stack Level 3 Stack Level 4 Stack Level 5
On-chip Program Memory
Fig. 3 Program counter organization
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Address
R PAGE registers
IOC PAGE registers
00 01
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R0 R1 R2 R3 R4 R5 R6 (TCC) (PC) (Status) (RSR) (Port5) (Port6) Reserve Reserve Reserve Reserve Reserve Reserve Reserve Res RF (Interrupt Status) IOCF IOCB IOCC IOCD IOC5 IOC6 CONT
Reserve (Control Register Reserve Reserve Reserve (I/O Port Control Register) (I/O Port Control Register) Reserve Reserve Reserve Reserve (Pull-down Registe (Open-drain Contro (Pull-high Control Registe
02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
(Interrupt Mask Registe
General Registers 2F Fig. 4 Data memory configuration
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4. R3 (Status Register)
7 RST 6 GP1 5 GP0 4 T 3 P 2 Z 1 DC 0 C
* Bit 7 (RST) Bit for reset type. Set to 1 if wake-up from sleep mode on pin change
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Set to 0 if wake up from other reset types * Bit6 ~ 5 (GP1 ~ 0) General purpose read/write bits. * Bit 4 (T) Time-out bit. Set to 1 with the "SLEP" and "WDTC" command, or during power up and reset to by WDT time-out. * Bit 3 (P) Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. * Bit 2 (Z) Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero. * Bit 1 (DC) Auxiliary carry flag * Bit 0 (C) Carry flag
5. R4 (RAM Select Register)
* Bits 7 ~ 6 are general-purpose read/write bits. See the configuration of the data memory in Fig. 4. * Bits 5 ~ 0 are used to select registers (address: 00~06, 0F~2F) in the indirect addressing mode.
6. R5 ~ R6 (Port 5 ~ Port 6)
* R5 and R6 are I/O registers. * Only the lower 4 bits of R5 are available. * The upper 4 bits of R5 are fixed to 0. * P63 is input only.
7. RF (Interrupt Status Register)
7 6 5 4 3 2 EXIF 1 ICIF 0 TCIF
"1" means interrupt request, and "0" means no interrupt occurs. * Bits 7 ~ 3 Not used. * Bit 2 (EXIF) External interrupt flag. Set by falling edge on /INT pin, reset by software. * Bit 1 (ICIF) Port 6 input status changed interrupt flag. Set when Port 6 input changes, reset by software. * Bit 0 (TCIF) TCC overflowing interrupt flag. Set when TCC overflows, reset by software.
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* RF can be cleared by instruction but cannot be set. * IOCF is the interrupt mask register. * Note that the result of reading RF is the "logic AND" of RF and IOCF.
8. R10 ~ R2F
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* All of these are the 8-bit general-purpose registers.
4.2 Special Purpose Registers
1. A (Accumulator)
* Internal data transfer, or instruction operand holding * It cannot be addressed.
2. CONT (Control Register)
7 6 INT 5 TS 4 TE 3 PAB 2 PSR2 1 PSR1 0 PSR0
* Bit 7 Not used. * Bit 6 (INT) Interrupt enable flag 0: masked by DISI or hardware interrupt 1: enabled by ENI/RETI instructions * Bit 5 (TS) TCC signal source 0: internal instruction cycle clock, P62 is a bi-directional I/O pin. 1: transition on TCC pin * Bit 4 (TE) TCC signal edge 0: increment if the transition from low to high takes place on TCC pin 1: increment if the transition from high to low takes place on TCC pin * Bit 3 (PAB) Prescaler assignment bit. 0: TCC 1: WDT * Bit 2 (PSR2) ~ 0 (PSR0) TCC/WDT prescaler bits. PSR2 0 0 0 0 1 1 1 1 PSR1 0 0 1 1 0 0 1 1 PSR0 0 1 0 1 0 1 0 1 TCC Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
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WDT Rate 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
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* CONT register is both readable and writable.
3. IOC5 ~ IOC6 (I/O Port Control Register)
* "1" put the relative I/O pin into high impedance, while "0" defines the relative I/O pin as output. * Only the lower 4 bits of IOC5 are available to be defined.
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* IOC5 and IOC6 registers are both readable and writable.
4. IOCB (Pull-down Control Register)
7 * Bit 7 Not used. 0: Enable internal pull-down 1: Disable internal pull-down * Bit 6 (/PD6) Control bit used to enable the pull-down of P62 pin. * Bit 5 (/PD5) Control bit is used to enable the pull-down of P61 pin. * Bit 4 (/PD4) Control bit is used to enable the pull-down of P60 pin. * Bit 3 Not used * Bit 2 (/PD2) Control bit is used to enable the pull-down of P52 pin. * Bit 1 (/PD1) Control bit is used to enable the pull-down of P51 pin. * Bit 0 (/PD0) Control bit is used to enable the pull-down of P50 pin. * IOCB Register is both readable and writable. 6 /PD6 5 /PD5 4 /PD4 3 2 /PD2 1 /PD1 0 /PD0
5. IOCC (Open-drain Control Register)
7 OD7 6 OD6 5 OD5 4 OD4 3 2 OD2 1 OD1 0 OD0
* Bit 7 (OD7) Control bit is used to enable the open-drain of P67 pin. 0: Disable open-drain output 1: Enable open-drain output * Bit 6 (OD6) Control bit is used to enable the open-drain of P66 pin. * Bit 5 (OD5) Control bit is used to enable the open-drain of P65 pin. * Bit 4 (OD4) Control bit is used to enable the open-drain of P64 pin. * Bit 3 Not used. * Bit 2 (OD2) Control bit is used to enable the open-drain of P62 pin. * Bit 1 (OD1) Control bit is used to enable the open-drain of P61 pin. * Bit 0 (OD0) Control bit is used to enable the open-drain of P60 pin. * IOCC Register is both readable and writable.
6. IOCD (Pull-high Control Register)
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7 /PH7 6 /PH6 5 /PH5 4 /PH4 3 2 /PH2 1 /PH1 0 /PH0
* Bit 7 (/PH7) Control bit is used to enable the pull-high of P67 pin. 0: Enable internal pull-high 1: Disable internal pull-high
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* Bit 6 (/PH6) Control bit is used to enable the pull-high of P66 pin. * Bit 5 (/PH5) Control bit is used to enable the pull-high of P65 pin. * Bit 4 (/PH4) Control bit is used to enable the pull-high of P64 pin. * Bit 3 Not used.
* Bit 2 (/PH2) Control bit is used to enable the pull-high of P62 pin. * Bit 1 (/PH1) Control bit is used to enable the pull-high of P61 pin. * Bit 0 (/PH0) Control bit used to enable the pull-high of P60 pin. * IOCD Register is both readable and writable.
7. IOCE (WDT Control Register)
7 WDTE 6 EIS 5 4 3 2 1 0 -
* Bit 7 (WDTE) Control bit used to enable Watchdog timer. 0: Disable WDT. 1: Enable WDT. WDTE is both readable and writable. * Bit 6 (EIS) Control bit is used to define the function of P60(/INT) pin. 0: P60, bi-directional I/O pin. 1: /INT, external interrupt pin. In this case, the I/O control bit of P60 (bit 0 of IOC6) must be set to "1". When EIS is "0", the path of /INT is masked. When EIS is "1", the status of /INT pin can also be read by way of reading Port 6 (R6). Refer to Fig. 7. EIS is both readable and writable. * Bit 5 ~ 0 Not used.
8. IOCF (Interrupt Mask Register)
7 6 5 4 3 2 EXIE 1 ICIE 0 TCIE
* Bit 7 ~ 3 Not used. * Individual interrupt is enabled by setting its associated control bit in the IOCF to "1". * Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Fig. 9. * Bit 2 (EXIE) EXIF interrupt enable bit.
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0: disable EXIF interrupt 1: enable EXIF interrupt * Bit 1 (ICIE) ICIF interrupt enable bit. 0: disable ICIF interrupt 1: enable ICIF interrupt
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* Bit 0 (TCIE) TCIF interrupt enable bit. 0: disable TCIF interrupt 1: enable TCIF interrupt * IOCF register is both readable and writable.
4.3 TCC/WDT & Prescaler
There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for the TCC only or the WDT only at the same time and the PAB bit of the CONT register is used to determine the prescaler assignment. The PSR0~PSR2 bits determine the ratio. The prescaler is cleared each time the instruction is written to TCC under TCC mode. The WDT and prescaler, when assigned to WDT mode, are cleared by the "WDTC" or "SLEP" instructions. Fig. 5 depicts the circuit diagram . * R1(TCC) is an 8-bit timer/counter. The clock source of TCC can be internal or external clock input (edge selectable from TCC pin). If TCC signal source is from internal clock, TCC will increase by 1 at every instruction cycle (without prescaler). Referring to Fig. 5, CLK=Fosc/2 or CLK=Fosc/4, depends on the CODE Option bit CLK. CLK=Fosc/2 is used if CLK bit is "0", and CLK=Fosc/4 is used if CLK bit is "1". If TCC signal source is from external clock input, TCC is increased by 1 at every falling edge or rising edge of TCC pin. * The watchdog timer is a free running on-chip RC oscillator. The WDT will keep running even when the oscillator driver has been turned off (i.e. in sleep mode). During normal operation or sleep mode, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled any time during normal mode by software programming. Refer to WDTE bit of IOCE register. Without prescaler, the WDT time-out period is approximately 18 ms1 (default).
4.4 I/O Ports
The I/O registers, both Port 5 and Port 6, are bi-directional tri-state I/O ports. Port 6 can be pulled-high
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: Vdd = 5V, set up time period = 16.5ms 30% Vdd = 3V, set up time period = 18ms 30%
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internally by software except P63. In addition, Port 6 can also have open-drain output by software except P63. Input status changed interrupt (or wake-up) function is available from Port 6. P50 ~ P52 and P60 ~ P62 pins can be pulled-down by software. Each I/O pin can be defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC6) except P63. The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits for Port 5 and Port 6 are shown in Fig 6,Fig.7 and fig. 8 respectively. www..com
Fig. 5 Block diagram of TCC and WDT
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PCRD
Q
P R C L
D CLK PCWR
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_ Q
PORT
Q _ Q
P R C L
D CLK PDWR
IOD
PDRD 0 1 M U X
*Pull-down is not shown in the figure.
Fig. 6 The circuit of I/O port and I/O control register for Port 5
PCRD
P QR _D Q CLK C L
PCW R
PORT B it 6 o f I O C E D R CLK C L Q _ Q 0 1 M U X
Q _ Q
P RD CLK C L
IO D PDW R
PDRD
T 10
D
P R
Q _ Q
CLK C L
*Pull-high (down), Open-drain are not shown in the figure.
Fig. 7 The circuit of I/O port and I/O control register for P60(/INT)
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Q _ Q
P RD CLK C L
PCW R
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PORT Q _ Q 0 1 P D R CLK C L IO D PDW R
M U X TIN PDRD
D
P R CLK C L
Q _ Q
*Pull-high (down), Open-drain are not shown in the figure.
Fig. 8 The circuit of I/O port and I/O control register for P61~P67
ICIE
D
P R C L
Q Interrupt _ Q ICIF ENI Instruction D P R Q Q _ Q P R C L D
CLK
CLK
_ CQ L
CLK
DISI Instruction Interrupt (W ake-up from SLEEP)
/SLEP
Next Instruction (W ake-up from SLEEP)
Fig. 9 Block diagram of I/O Port 6 with input change interrupt/wake-up
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Table 2 Usage of Port 6 input change wake-up/interrupt function Usage of Port 6 Input Status Change Wake-up/Interrupt (I) Wake-up from Port 6 Input Status Change (a) Before SLEEP 1. Disable WDT 2. Read I/O Port 6 (MOV R6,R6) 3. Execute "ENI" or "DISI" 4. Enable interrupt (Set IOCF.1) 5. Execute "SLEP" instruction (b) After Wake-up Interrupt vector (008H) 1. IF "ENI" 2. IF "DISI" Next instruction (II) Port 6 Input Status Change Interrupt 1. Read I/O Port 6 (MOV R6,R6) 2. Execute "ENI" 3. Enable interrupt (Set IOCF.1) 4. IF Port 6 change (interrupt) Interrupt vector (008H)
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4.5 RESET and Wake-up
1. RESET
Input Status Change (1) Power on reset. (2) /RESET pin input "low", or (3) WDT time-out (if enabled). The device is kept in a RESET condition for a period of approx. 18ms1 (one oscillator start-up timer period) after the reset is detected. Once the RESET occurs, the following functions are performed. Refer to Fig10.. * The oscillator is running, or will be started. * The Program Counter (R2) is set to all "0". * All I/O port pins are configured as input mode (high-impedance state). * The Watchdog timer and prescaler are cleared. * When power is switched on, the upper 3 bits of R3 are cleared. * The bits of the CONT register are set to all "1" except for the Bit 6 (INT flag). * The bits of the IOCB register are set to all "1". * The IOCC register is cleared. * The bits of the IOCD register are set to all "1". * Bit 7 of the IOCE register is set to "1", and Bits 4 and 6 are cleared. * Bits 0~2 of RF and bits 0~2 of IOCF register are cleared.
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Vdd = 5V, set up time period = 16.5ms 30% Vdd = 3V, set up time period = 18ms 30%
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The sleep (power down) mode is attained by executing the "SLEP" instruction. While entering sleep mode, WDT (if enabled) is cleared but keeps on running. The controller can be awakened by (1) External reset input on /RESET pin, (2) WDT time-out (if enabled), or
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(3) Port 6 input status changes (if enabled). The first two cases will cause the BJ8P508/153 to reset. The T and P flags of R3 can be used to determine the source of the reset (wake-up). The last case is considered the continuation of program execution and the global interrupt ("ENI" or "DISI" being executed) decides whether or not the controller branches to the interrupt vector following wake-up. If ENI is executed before SLEP, the instruction will begin to execute from the address 008H after wake-up. If DISI is executed before Only one of the Cases 2 and 3 can be enabled before entering the sleep mode. That is, [a] if Port 6 input status changed interrupt is enabled before SLEP , WDT must be disabled. By software. However, the WDT bit in the option register remains enabled. Hence, the BJ8P508/153 can be awakened only by Case 1 or 3. [b] if WDT is enabled before SLEP, Port 6 Input Status Change Interrupt must be disabled. Hence, the BJ8P508/153 can be awakened only by Case 1 or 2. Refer to the section on interrupt. If Port 6 Input Status Changed Interrupt is used to wake-up the BJ8P508/153 (Case [a] above), the following instructions must be executed before SLEP: MOV CONTW WDTC MOV IOW MOV MOV IOW ENI (or DISI) SLEP NOTE: 1. After waking up from the sleep mode, WDT is automatically enabled. The WDT enabled/disable operation after waking up from sleep mode should be appropriately defined in the software. 2. To avoid a reset from occurring when the Port 6 Input Status Changed Interrupt enters into interrupt vector or is used to wake-up the MCU, the WDT prescaler must be set above the 1:1 ratio. A, @xxxx1110b A, @0xxxxxxxb RE R6, R6 A, @00000x1xb RF ; Select WDT prescaler, prescaler must set over 1:1 ; Clear WDT and prescaler ; Disable WDT ; Read Port 6 ; Enable Port 6 input change interrupt ; Enable (or disable) global interrupt ; Sleep
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Table 3 The Summary of the Initialized Register Values
Address N/A
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Name IOC5
N/A
IOC6
0x05
P5
0x06
P6
N/A
CONT
0x00
R0(IAR)
0x01
R1(TCC)
0x02
R2(PC)
0x03
R3(SR)
0x04
R4(RSR)
0x0F 0x0B
RF(ISR) IOCB
Reset Type Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name PSR0 Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On
Bit 7 X 0 0 0 C67 1 1 P X 1 P P P67 1 P P X 1 1 P U P P 0 0 P 0 0 P RST 0 0 1 GP1 U P P X 0 0 0 X 1
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Bit 6 X 0 0 0 C66 1 1 P X 1 P P P66 1 P P INT 0 0 0 U P P 0 0 P 0 0 P GP1 0 0 P GP0 U P P X 0 0 0 /PD6 1
Bit 5 X 0 0 0 C65 1 1 P X 1 P P P65 1 P P TS 1 1 P U P P 0 0 P 0 0 P GP0 0 0 P U P P X 0 0 0 /PD5 1
Bit 4 X 0 0 0 C64 1 1 P X 1 P P P64 1 P P TE 1 1 P U P P 0 0 P 0 0 P T 1 t t U P P X 0 0 0 /PD4 1
Bit 3 C53 1 1 P C63 1 1 P P53 1 P P P63 1 P P PAB 1 1 P U P P 0 0 P 0 0 N P 1 t t U P P X 0 0 0 /PD3 1
Bit 2 C52 1 1 P C62 1 1 P P52 1 P P P62 1 P P PSR2 1 1 P U P P 0 0 P 0 0 P Z U P P U P P EXIF 0 0 P /PD2 1
Bit 1 C51 1 1 P C61 1 1 P P51 1 P P P61 1 P P PSR1 1 1 P U P P 0 0 P 0 0 P DC U P P U P P ICIF 0 0 N /PD1 1
Bit 0 C50 1 1 P C60 1 1 P P50 1 P P P60 1 P P
1 1 P U P P 0 0 P 0 0 P C U P P U P P TCIF 0 0 P /PD0 1
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Address Reset Type Bit 7 Bit 6 Wake-Up from Pin Change P P Bit Name OD7 OD6 0 0 Power-On IOCC /RESET and WDT 0 0 Wake-Up from Pin Change P P Bit Name /PH7 /PH6 Power-On 1 1 IOCD /RESET and WDT 1 1 Wake-Up from Pin Change P P Bit Name WDTE EIS Power-On 1 0 IOCE /RESET and WDT 1 0 Wake-Up from Pin Change 1 P Bit Name X X Power-On 1 1 IOCF /RESET and WDT 1 1 Wake-Up from Pin Change 1 1 Bit Name Power-On U U R10~R2F /RESET and WDT P P Wake-Up from Pin Change P P Name Bit 5 P OD5 0 0 P /PH5 1 1 P X 1 1 1 X 1 1 1 U P P Bit 4 P OD4 0 0 P /PH4 1 1 P X 1 1 1 X 1 1 1 U P P Bit 3 P X 0 0 P X 1 1 P X 1 1 1 X 1 1 1 U P P Bit 2 P OD2 0 0 P /PH2 1 1 P X 1 1 1 EXIE 0 0 P U P P Bit 1 P OD1 0 0 P /PH1 1 1 P X 1 1 1 ICIE 0 0 P U P P Bit 0 P OD0 0 0 P /PH0 1 1 P X 1 1 1 TCIE 0 0 P U P P
0x0C
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0x0D
0x0E
0x0F
0x10~0x2F
X: not used. U: unknown or don't care. -: not defined P: previous value before reset. t: check Table 4 N: Monitors interrupt operation status; 1 = running; P = not running
2. /RESET Configure
Refer to Fig. 10 When the RESET bit in the OPTION word is programmed to 0, the external /RESET is enabled. When programmed to 1, the internal /RESET is enabled, tied to the internal Vdd and the pin is defined as P63.
3. The status of RST, T, and P of STATUS register
A RESET condition is initiated by the following events: 1. A power-on condition, 2. A high-low-high pulse on /RESET pin, and 3. Watchdog timer time-out. The values of RST, T and P, listed in Table 4 are used to check hoe the processor wakes up. Table 5 shows the events which may affect the status of RST, T and P.
This specification is subject to change without prior notice.
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Table 4 The Values of RST, T and P after RESET Reset Type Power on /RESET during Operating mode /RESET wake-up during SLEEP mode WDT during Operating mode WDT wake-up during SLEEP mode Wake-Up on pin change during SLEEP mode *P: Previous status before reset Table 5 The Status of RST, T and P being Affected by Events Event Power on WDTC instruction WDT time-out SLEP instruction Wake-Up on pin change during SLEEP mode *P: Previous value before reset RST 0 *P 0 *P 1 T 1 1 0 1 1 P 1 1 *P 0 0 RST 0 0 0 0 0 1 T 1 *P 1 0 0 1 P 1 *P 0 P 0 0
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VDD
Oscillator
D CLK CLR
Q
CLK
Power-on Reset
Voltage Detector
WDTE
WDT
WDT Timeout
Setup Time
RESET
/RESET
Fig. 10 Block Diagram of Controller Rese
This specification is subject to change without prior notice.
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The BJ8P508/153 has three falling-edge interru pts as listed below: (1) TCC overflow interrupt (2) Port 6 Input Status Change Interrupt
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(3) External interrupt [(P60, /INT) pin]. Before the Port 6 Input Status Changed Interrupt is enabled, reading Port 6 (e.g. "MOV R6,R6") is necessary. Each pin of Port 6 will have this feature if its status changes. Any pin configured as output or P60 pin configured as /INT, is excluded from this function. The Port 6 Input Status Changed Interrupt can wake up the BJ8P508/153 from sleep mode if Port 6 is enabled prior to going into the sleep mode by executing SLEP instruction. When the chip wakes-up, the controller will continue to execute the program in-line if the global interrupt is disabled. If the global interrupt is enabled, it will branch to the RF is the interrupt status register that records the interrupt requests in the relative flags/bits. IOCF is an interrupt mask register. The global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. When one of the interrupts (enabled) occurs, the next instruction will be fetched from address 008H. Once in the interrupt service routine, the source of an interrupt can be determined by polling the flag bits in RF. The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine before interrupts are enabled to avoid recursive interrupts. The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the status of its mask bit or the execution of ENI. Note that the outcome of RF will be the logic AND of RF and IOCF (refer to Fig. 11). The RETI instruction ends the interrupt routine and enables the global interrupt ( the execution of ENI). When an interrupt is generated by the INT instruction (enabled), the next instruction will be fetched from address 001H.
This specification is subject to change without prior notice.
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OTP ROM
VCC
D /IRQn CLK
P R C L
Q _ Q RFRD
IRQn INT IRQm ENI/DISI
RF
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Q _ Q
P R C L
D CLK IOCFWR
IOD
IOCF /RESET
IOCFRD
RFWR
Fig. 11 Interrupt input
4.7 Oscillator
1. Oscillator Modes
The BJ8P508/153 can be operated in four different oscillator mod es, such as Internal RC oscillato mode (IRC), External RC oscillator mode(ERC), High XTAL oscillator mode(HXT), and Low XTAL oscillator mode(LXT). User can select one of them by programming OCS1 and OSC2 in the CODE Option register. Table 6 depicts how these four modes are defined. The up-limited operation frequency of crystal/resonator on the different VDDs is listed in Table 7. Table 6 Oscillator Modes defined by OSC1 and OSC2 Mode IRC(Internal RC oscillator mode) ERC(External RC oscillator mode) HXT(High XTAL oscillator mode) LXT(Low XTAL oscillator mode) OSC1 1 1 0 0 OSC2 1 0 1 0
The transient point of system frequency between HXT and LXY is around 400 KHz.
This specification is subject to change without prior notice.
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Table 7 The summary of maximum operating speeds Conditions Two cycles with two clocks
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VDD 2.3 3.0 5.0
Fxt max.(MHz) 4.0 8.0 20.0
2. Crystal Oscillator/Ceramic Resonators(XTAL)
BJ8P508/153 can be driven by an external clock signal through the OSCI pin as shown in Fig. 12
OSCI OSCO BJ8P508/153
Ext. Clock
Fig. 12 Circuit for External Clock Inpu In most applications, pin OSCI and pin OSCO can be connected with a crystal or ceramic resonator to generate oscillation. Fig. 13 depicts such circuit. The same thing applies whether it is in the HXT mode or in the LXT mode. Table 8 provides the recommended values of C1 and C2. Since each resonator has its own attribute, user should refer to its specification for appropriate values of C1 and C2. RS, a serial resistor, may be necessary for AT strip cut crystal or low frequency mode
C1 OSCI XTAL
BJ8P508/153 OSCO
RS
C2
Fig. 13 Circuit for Crystal/Resonato Table 8 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonators
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Oscillator Type Ceramic Resonators Frequency Mode HXT Frequency 455 kHz 2.0 MHz 4.0 MHz 32.768kHz
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C1(pF) 100~150 20~40 10~30 25 25 25 20~40 15~30 15 15
C2(pF) 100~150 20~40 10~30 15 25 25 20~150 15~30 15 15
LXT Crystal Oscillator HXT
100KHz 200KHz 455KHz 1.0MHz 2.0MHz 4.0MHz
1. The value of capacitors (C1, C2) is for reference.
3. External RC Oscillator Mode
For some applications that do not need to have its timing to be calculated precisely, the RC oscillator (Fig. 16) offers a lot of cost savings. Nevertheless, it should be noted that the frequency of the RC oscillator is influenced by the supply voltage, the values of the resistor (Rext), the capacitor (Cext), and even the operation temperature. Moreover, the frequency also changes slightly from one chip to another due to the manufacturing process variation. In order to maintain a stable system frequency, the values of the Cext should not be less than 20pF, and that the value of Rext should not be greater than 1 M ohm. If they cannot be kept in this range, the frequency is easily affected by noise, humidity, and leakage. The smaller the Rext in the RC oscillator, the faster its frequency will be. On the contrary, for very low Rext values, for instance, 1 K&, the oscillator becomes unstable because the NMOS cannot discharge the current of the capacitance correctly. Based on the reasons above, it must be kept in mind that all of the supply voltage, the operation temperature, the components of the RC oscillator, the package types, the way the PCB is layout, will affect the system frequency.
This specification is subject to change without prior notice.
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Vcc Rext
OSCI
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Cext BJ8P508/153
Fig.14 Circuit for External RC Oscillator Mode
Table 9 RC Oscillator Frequencies
Cext 20 pF
100 pF
300 pF
Rext 3.3k 5.1k 10k 100k 3.3k 5.1k 10k 100k 3.3k 5.1k 10k 100k
Average Fosc 5V,25C 3.92 MHz 2.67 MHz 1.4 MHz 150 KHz 1.4 MHz 940 KHz 476 KHz 50 KHz 595 KHz 400 KHz 200 KHz 20.9 KHz
Average Fosc 3V,25C 3.63MHz 2.6 MHz 1.4 MHz 156 KHz 1.33 MHz 917 KHz 480 KHz 52 KHz 570 KHz 384 KHz 203 KHz 20 KHz
1. Measured on DIP packages. 2. Design reference only 3. The frequency drift is about 30%
4. Internal RC Oscillator Mode
BJ8P508/153 offer a versatile internal RC mode with default frequency value of 4MHz.Internal RC
oscillator mode still has other frequencies 8MHz, 1MHz, and 455KHz and can be set by OPTION bits, RCM1 and RCM0. All these four main frequencies can be calibration by programming the OPTION bits, CAL0~CAL2. Table 10 describes the BJ8P508/153 voltage, nternal RC drift with the variation of
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Table 10 Internal RC Drift Rate (Ta=25C , VDD=5 V 5%, VSS=0V) Internal RC 8MHz 4MHz 1MHz 455kHz Drift Rate Temperature (0C~70C) 3% 3% 3% 3% Voltage (2.3V~5.5V) 5% 5% 5% 5% Process 10% 5% 10% 10% Total 18% 13% 18% 18%
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4.8 Code Option Register
The BJ8P508/153 has one CODE option word that is not a part of the normal program memory. The option bits cannot be accessed during normal program execution. Code Option Register and Customer ID Register arrangement distribution: Word 0 Bit12~Bit0 Word1 Bit1~Bit0 Word 2 Bit12~Bit0
Code Option Register (Word 0)
WORD 0 Bit12 /RESET Bit11 /ENWDT Bit10 CLKS Bit9 OSC1 Bit8 OCS0 Bit7 CS Bit6 SUT1 Bit5 SUT0 Bit4 TYPE Bit3 RCOUT Bit2 C2 Bit1 C1 Bit0 C0
* Bit 12 (/RESET): Define pin7 as a reset pin. 0: /RESET enable 1: /RESET disable * Bit 11 (/ENWTD): Watchdog timer enable bit. 0: Enable 1: Disable This bit must enable and the WDTE reg. (IOCE reg. bit 6) must disable when port 6 pin change wake up function is used. * Bit 10 (CLKS): Instruction period option bit. 0: two oscillator periods. 1: four oscillator periods. Refer to the section of Instruction Set. * Bit 9 and Bit 8 ( OSC1 and OSC0 ): Oscillator Modes Selection bits. Table 11 Oscillator Modes defined by OSC1 and OSC0 Mode IRC(Internal RC oscillator mode) ERC(External RC oscillator mode) HXT(High XTAL oscillator mode)
This specification is subject to change without prior notice.
OSC1 1 1 0
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OSC0 1 0 1
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LXT(Low XTAL oscillator mode) * Bit 7 (CS): Code Security Bit 0: Security On 1: Security Off
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0
0
: The transient point of system frequency between HXT and LXY is around 400 KHz.
* Bit6 and Bit5 ( SUT1 and SUT0 ): Set-Up Time of device bits. Table 12 Set-Up Time of device Programming SUT1 1 1 0 0 SUT0 1 0 1 0 *Set-Up Time 18 ms 4.5 ms 288 ms 72 ms
* Theoretical values, for reference only
* Bit 4 (Type): Type selection for BJ8P156AP TYPE 0 1 RCOUT 0 1 C2,C1,C0 must be set to "1" ONLY. Series BJ8P508/153 X Pin Function P64 OSCO
* Bit 3 (RCOUT): A selecting bit of Oscillator output or I/O port.
* Bit 2, Bit 1, and Bit 0 ( C2, C1, C 0 ): Calibrator of internal RC mode Bit 3
Code Option Register (Word 1)
WORD1 Bit1 RCM1 RCM 1 1 1 0 0 RCM 0 1 0 1 0 Bit0 RCM0 *Frequency(MHz) 4 8 1 455kHz
Bit 1, and Bit 0 ( RCM1, RCM0): RC mode selection bits
Customer ID Register (Word 2)
Bit 12~Bit 0 XXXXXXXXXXXXX Bit 12~ 0 : Customer's ID code
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OTP ROM 4.9 Power On Considerations
Any microcontroller is not guaranteed to start to operate properly before the power supply stabilizes at its steady state. Under customer application, when power is OFF, Vdd must drop to below 1.8V and remains
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OFF
for
10us
before
power
can
be
switched
ON
again.
This
way,
the
BJ8P508/153 will reset and work normally. The extra external reset circuit will work well if Vdd can rise at very fast speed (50 ms or less). However, under most cases where critical applications are involved, extra devices are required to assist in solving the power-up problems.
4.10 Programmable Oscillator Set-Up Time
The Option word contains SUT0 and SUT1 which can be used to define the oscillator set up time. Theorically, the range is from 4.5 ms to 72 ms. For most of crystal or ceramic resonators, the lower the operation frequency is, the longer the Set-up time may be required. Table 12 describes the values of Oscillator Set-Up Time.
4.11 External Power On Reset Circuit
The circuit shown in Fig 17 implements an external RC to produce the reset pulse. The pulse width (time constant) should be kept long enough for Vdd to reach minimum operation voltage. This circuit is used when the power supply has slow rise time. Because the current leakage from the /RESET pin is about 5A, it is recommended that R should not be great than 40 K. In this way, the voltage in pin /RESET will be held below 0.2V. The diode (D) acts as a short circuit at the moment of power down. The capacitor C, will discharged rapidly and fully. Rl, the current-limited resistor, will prevent high current
Vdd /RESET BJ8P508/153 Rin C R D
Fig. 15 External Power-Up Reset Circuit
4.12 Residue-Voltage Protection
When battery is replaced, device power
31
(Vdd)
is
taken
off
but
residue-voltage
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OTP ROM
residue-voltage may trips below Vdd minimum, but not to zero. This condition may cause a poor power on reset. Fig.18 and Fig. 19 show how to build a residue-voltage protection circuit.
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Vdd 33K BJ8P508/153 /RESET 100K 1N4684 Q1 10K
Vdd
Fig. 16 Circuit 1 for the residue voltage protection
Vdd R1 BJ8P508/153 /R E S E T R3 R2 Q1
V dd
Fig.17 Circuit 2 for the residue voltage protection
4.13 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more operands. Normally, all instructions are executed within one single instruction cycle (one instruction consists of 2 oscillator periods), unless the program counter is changed by instructio "MOV R2,A"
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"ADD R2,A", or by instructions of arithmetic or logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6", "CLR R2", ). In this case, the execution takes two instruction cycles. If for some reasons, the specification of the instruction cycle is not suitable for certain applications, try modifying the instruction as follows:
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(A) Modify one instruction cycle to consist of 4 oscillator periods. (B) Execute within two instruction cycles the "JMP", "CALL", "RET", "RETL", "RETI" commands, or the conditional skip ("JBS", "JBC", "JZ", "JZA", "DJZ", "DJZA") which were tested to be true. The instructions that are written to the program counter, should also take two instruction cycles. The Case (A) is selected by the CODE Option bit, called CLKS. One instruction cycle will consist of two oscillator clocks if CLKS is low, and four oscillator clocks if CLKS is high. Note that once the 4 oscillator periods within one instruction cycle is selected under Case (A), th internal clock source to TCC should be CLK=Fosc/4 ,instead of Fosc/ 2 as illustrated in Fig. 5. In addition, the instruction set has the following features: (1) Every bit of any register can be set, cleared, or tested directly. (2) The I/O register can be regarded as general register. That is, the same instruction can operate on I/O register. The symbol "R" represents a register designator that specifies which one of the registers (including operational registers and general purpose registers) is to be utilized by the instruction. "b" represents a bit field designator that selects the value for the bit which is located in the register "R", and affects the operation. "k" represents an 8 or 10-bit constant or literal value.
INSTRUCTION BINARY 0 0000 0000 0000 0 0000 0000 0001 0 0000 0000 0010 0 0000 0000 0011 0 0000 0000 0100 0 0000 0000 rrrr 0 0000 0001 0000 0 0000 0001 0001 0 0000 0001 0010 0 0000 0001 0011 0 0000 0001 0100 0 0000 0001 rrrr 0 0000 01rr rrrr 0 0000 1000 0000 0 0000 11rr rrrr
HEX 0000 0001 0002 0003 0004 000r 0010 0011 0012 0013 0014 001r 00rr 0080 00rr
MNEMONIC NOP DAA CONTW SLEP WDTC IOW R ENI DISI RET RETI CONTR IOR R MOV R,A CLRA CLR R
OPERATION No Operation Decimal Adjust A A CONT 0 WDT, Stop oscillator 0 WDT A IOCR Enable Interrupt Disable Interrupt PC [Top of Stack] [Top of Stack] PC, Enable Interrupt CONT A IOCR A A R 0 A 0 R
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STATUS AFFECTED None C None T,P T,P None None None None None None None None Z Z
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OTP ROM
0 0001 00rr 0 0001 01rr 0 0001 10rr 0 0001 11rr 0 0010 00rr 0 0010 01rr 0 0010 10rr 0 0010 11rr www..com 0 0011 00rr 0 0011 01rr 0 0011 10rr 0 0011 11rr 0 0100 00rr 0 0100 01rr 0 0100 10rr 0 0100 11rr 0 0101 00rr 0 0101 01rr 0 0101 10rr 0 0101 11rr 0 0110 00rr 0 0110 01rr 0 0110 10rr 0 0110 11rr 0 0111 00rr 0 0111 01rr 0 0111 10rr 0 0111 11rr 0 100b bbrr 0 101b bbrr 0 110b bbrr 0 111b bbrr 1 00kk kkkk 1 01kk kkkk 1 1000 kkkk 1 1001 kkkk 1 1010 kkkk 1 1011 kkkk 1 1100 kkkk 1 1101 kkkk 1 1110 0000 1 1111 kkkk rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk 0001 kkkk 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr 04rr 04rr 05rr 05rr 05rr 05rr 06rr 06rr 06rr 06rr 07rr 07rr 07rr 07rr 0xxx 0xxx 0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1E01 1Fkk SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R COMA R COM R INCA R INC R DJZA R DJZ R RRCA R RRC R RLCA R RLC R SWAPA R SWAP R JZA R JZ R BC R,b BS R,b JBC R,b JBS R,b CALL k JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k INT ADD A,k R-A A R R-A R-1 A R-1 R A ( VR A A ( VR R A&R A A&R R AR A AR R A+R A A+R R R A R R /R A /R R R+1 A R+1 R R-1 A, skip if zero R-1 R, skip if zero R(n) A(n-1),R(0) C, C A(7) R(n) R(n-1),R(0) C, C R(7) R(n) A(n+1),R(7) C, C A(0) R(n) R(n+1),R(7) C, C R(0) R(0-3) A(4-7),R(4-7) A(0-3) R(4-7) R(0-3) R+1 A, skip if zero R+1 R, skip if zero 0 R(b) 1 R(b) if R(b)=0, skip if R(b)=1, skip [SP],(Page, k) PC PC+1 (Page, k) PC k A A(k A A&k A Ak A k A,[Top of Stack] PC k-A A PC+1 [SP],001H PC k+A A Z,C,DC Z,C,DC Z Z Z Z Z Z Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z None None C C C C None None None None None None None None None None None Z Z Z None Z,C,DC None Z,C,DC
This instruction is applicable to IOC5~IOC6, IOCB~IOCF only. This instruction is not recommended for RF operation. This instruction cannot operate under RF.
This specification is subject to change without prior notice.
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OTP ROM 4.14 Timing Diagrams
AC Test Input/Output Waveform
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2.4 2.0 0.8 0.4
TEST POINTS
2.0 0.8
AC Testing : Input is driven at 2.4V for logic "1",and 0.4V for logic "0".Timing measurements are made at 2.0V for logic "1",and 0.8V for logic "0".
RESET Timing (CLK="0")
NOP
Instruction 1 Executed
CLK
/RESET
Tdrh
TCC Input Timing (CLKS="0")
Tins
CLK
TCC
Ttcc
This specification is subject to change without prior notice.
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5. ABSOLUTE MAXIMUNM RATINGS
Items Temperature under bias
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Rating 0C to 70C -65C to 150C -0.3V to +6.0V -0.3V to +6.0V
Storage temperature Input voltage
Output voltage
This specification is subject to change without prior notice.
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6. ELECTRICAL CHARACTERISTIC
6.1 DC Electrical Characteristic
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Ta= 0C ~ 70 C, VDD= 5.0V5%, VSS= 0V )
Parameter Condition Min XTAL: VDD to 2.3V Two cycle with two clocks DC XTAL: VDD to 3V Two cycle with two clocks DC XTAL: VDD to 5V Two cycle with two clocks DC RC: VDD to 5V R: 5K&, C: 39 pF F-30% Input Leakage Current for input pins VIN = VDD, VSS Input High Voltage (VDD=5.0V) Ports 5, 6 2.0 Input Low Voltage (VDD=5.0V) Ports 5, 6 Input High Threshold Voltage (VDD=5.0V) /RESET, TCC (Schmitt trigger) 2.0 Input Low Threshold Voltage (VDD=5.0V) /RESET, TCC (Schmitt trigger) Clock Input High Voltage (VDD=5.0V) OSCI 2.5 Clock Input Low Voltage (VDD=5.0V) OSCI Input High Voltage (VDD=3.0V) Ports 5, 6 1.5 Input Low Voltage (VDD=3.0V) Ports 5, 6 Input High Threshold Voltage (VDD=3.0V) /RESET, TCC (Schmitt trigger) 1.5 Input Low Threshold Voltage (VDD=3.0V) /RESET, TCC (Schmitt trigger) Clock Input High Voltage (VDD=3.0V) OSCI 1.5 Clock Input Low Voltage (VDD=3.0V) OSCI Output High Voltage (Ports 5, 6) IOH = -12.0 mA 2.4 (P60~P63, P66~P67 are Schmitt trigger) Output Low Voltage (P50~P53, P60~P63, P66~P67), (P60~P63, P66~P67 are IOL = 12.0 mA Schmitt trigger) Output Low Voltage (P64,P65) IOL = 16.0 mA Pull-high current Pull-high active, input pin at VSS -50 Pull-down current Pull-down active, input pin at VDD 20 All input and I/O pins at VDD, Power down current output pin floating, WDT disabled All input and I/O pins at VDD, Power down current output pin floating, WDT enabled /RESET= 'High' Fosc=32KHz Operating supply current(VDD=3V) 15 (Crystal type,CLKS="0"), at two clocks output pin floating, WDT disabled /RESET= 'High', Fosc=32KHz Operating supply current (VDD=3V) (Crystal type,CLKS="0"), at two clocks output pin floating, WDT enabled /RESET= 'High', Fosc=4MHz Operating supply current(VDD=5.0V) (Crystal type, CLKS="0"), At two clocks output pin floating /RESET= 'High', Fosc=10MHz Operating supply current(VDD=5.0V) (Crystal type, CLKS="0"), at two clocks output pin floating Typ Max 4.0 8.0 20.0 F+30% 1 0.8 0.8 1.0 0.4 0.4 0.6 Unit MHz MHz MHz KHz A V V V V V V V V V V V V V 0.4 0.4 -240 120 V V A A
Symbol Fxt Fxt Fxt ERC IIL VIH1 VIL1 VIHT1 VILT1 VIHX1 VILX1 VIH2 VIL2 VIHT2 VILT2 VIHX2 VILX2
1500
VOL1 VOL2 IPH IPD ISB1 ISB2 ICC1 ICC2
-100 50
15 19
30 35 2.0 4.0
A A mA mA
ICC3 ICC4
* These parameters are characterizes and tested. * Data in the Minimum, Typical, Maximum("Min","Typ","Max") column are based on characterization results at 25 . This data is for design guidance and is tested.
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BJ8P508/153
OTP ROM 6.2 AC Electrical Characteristic
(Ta=0C ~ 70 C, VDD=5V5%, VSS=0V)
Symbol Dclk Tins www..com Ttcc Tdrh Trst Twdt1* Twdt2* Twdt3* Twdt4* Tset Thold Tdelay Parameter Input CLK duty cycle Instruction cycle time (CLKS="0") TCC input period Device reset hold time /RESET pulse width Watchdog timer period Watchdog timer period Watchdog timer period Watchdog timer period Input pin setup time Input pin hold time Output pin delay time Cload=20pF Ta = 25C TXAL,SUT1,SUT0=1,1 Ta = 25C Ta = 25C SUT1,SUT0=1,1 Ta = 25C SUT1,SUT0=1,0 Ta = 25C SUT1,SUT0=0,1 Ta = 25C Crystal type RC type Conditions Min 45 100 500 (Tins+20)/N* 17.6-30% 2000 17.6-30% 4.5-30% 288-30% 72-30% 17.6 4.5 288 72 0 20 50 17.6+30% 4.5+30% 288+30% 72+30% 17.6 17.6+30% Typ 50 Max 55 DC DC Unit % ns ns ns ms ns ms ms ms ms ns ns ns
* Twdt1: The Option word (SUT1,SUT0) is used to define the oscillator Set-Up time. In Crystal mode the WDT timeout length is the same as set-up time(18ms). * Twdt2: The Option word (SUT1,SUT0) is used to define the oscillator Set-Up time. In Crystal mode the WDT timeout length is the same as set-up time(4.5ms). * Twdt3: The Option word (SUT1,SUT0) is used to define the oscillator Set-Up time. In Crystal mode the WDT timeout length is the same as set-up time(288ms). * Twdt4: The Option word (SUT1,SUT0) is used to define the oscillator Set-Up time. In Crystal mode the WDT timeout length is the same as set-up time(72ms). * These parameters are characterizes but not tested. * Data in the Minimum, Typical, Maximum("Min","Typ","Max") column are based on characterization results at 25 . This data is for design guidance and is not tested.
* N= selected prescaler ratio. * The duration of watch dog timer is determined by option code (bit6,bit5)
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OTP ROM 6.3 Device Characteristic
The graphs provided in the following pages were derived based on a limited number of samples and are shown here for reference only. The device characteristic illustrated herein are not guaranteed for it accuracy. In some graphs, the data maybe out of the specified warranted operating range.
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Vih max (-40 Vih typ 25 Vih min (-40
to 85 )
to 85
)
Vil max (-40 Vil typ 25 Vil min (-40
to 85 )
to 85 )
Fig. 18 Vih, Vil of P60~P63, P66, P67 vs. VDD
This specification is subject to change without prior notice.
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OTP ROM
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Max (-40 to 85 ) T yp 25
Min(-40
to 85
)
Fig. 19 Vth (Threshold voltage) of P50~P53, P64~P65 vs. VDD
Max 70 Min 70 T yp 25 T yp 25
Min 0
Min 0
Fig. 20 Port5 and Port6 Voh vs. Ioh, VDD=5V
This specification is subject to change without prior notice. 40
Fig. 21 Port5 and Port6 Voh vs. Ioh, VDD=3V
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OTP ROM
Max 0
Max 0
Typ 25
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Min 70
T yp 25
Min 70
Fig. 22 Port5, Port6.0~Port6.3 and Port6.6~Port6.7 Vol vs. Iol, VDD=5V
Fig. 23 Port5, Port6.0~Port6.3 and Port6.6~Port6.7 Vol vs. Iol, VDD=3V
This specification is subject to change without prior notice.
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OTP ROM
Vol/Iol (VDD=5V)
Max 0
Max 0
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T yp 25
T yp 25
Min 70 Min 70
Vol (Volt)
Fig. 24 Port6.4 and Port6.5 Vol vs. Iol, VDD=5V
Fig. 25 Port6.4 and Port6.5 Vol vs. Iol, VDD=3V
This specification is subject to change without prior notice.
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OTP ROM
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Max 70
T yp 25
Min 0
Fig. 26 WDT time out period vs. VDD, perscaler set to 1:1
This specification is subject to change without prior notice.
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OTP ROM
R = 3.3K
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R = 5.1K
R = 10K
R = 100K
Fig. 27 Typical RC OSC Frequency vs. VDD (Cext=100pF, Temperature at 25 )
Fig. 28 Typical RC OSC Frequency vs. Temperature (R and C are ideal components)
This specification is subject to change without prior notice.
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OTP ROM
OSC = 8M Hz
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OSC = 4M Hz
OSC = 1M Hz OSC = 455K Hz
Fig. 29 Internal RC OSC Frequency vs. Temperature, VDD=5V
IRC OSC Frequency (VDD=3V)
OSC = 8M Hz
OSC = 4M Hz
OSC = 1M Hz OSC = 455K Hz
Temperature ( )
Fig. 30 Internal RC OSC Frequency vs. Temperature, VDD=3V
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OTP ROM
Four conditions exist with the Operating Current ICC1 to ICC4. These conditions are as follows: ICC1: VDD=3V, Fosc=32K Hz, 2 clocks, WDT disable ICC2: VDD=3V, Fosc=32K Hz, 2 clocks, WDT enable ICC3: VDD=5V, Fosc=4M Hz, 2 clocks, WDT enable ICC4: VDD=5V, Fosc=10M Hz, 2 clocks, WDT enable
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Typical ICC1 and ICC2 vs. Temperature
T yp ICC2 T yp ICC1
Temperature (
)
Fig. 31 Typical operating current (ICC1 and ICC2) vs. Temperature
Maximum ICC1 and ICC2 vs. Temperature
Max ICC2
Max ICC1
This specification is subject to change without prior notice.
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OTP ROM
Fig. 32 Maximum operating current (ICC1 and ICC2) vs. Temperature
Typical ICC3 and ICC4 vs. Temperature
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T yp ICC4
T yp ICC3
Fig. 33 Typical operating current (ICC3 and ICC4) vs. Temperature
Maximum ICC3 and ICC4 vs. Temperature
Max ICC4
Max ICC3
Temperature ( )
Fig. 34 Maximum operating current (ICC3 and ICC4) vs. Temperature
This specification is subject to change without prior notice.
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OTP ROM
Two conditions exist with the Standby Current ISB1 and ISB2. These conditions are as follows ISB1: VDD=5V, WDT disable ISB2: VDD=5V, WDT enable
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Typical ISB1 and ISB2 vs. Temperature
T yp ISB2
T yp ISB1
Temperature ( )
Fig. 35 Typical standby current (ISB1 and ISB2) vs. Temperature
Maximum ISB1 and ISB2 vs. Temperature
T yp ISB2
T yp ISB1
Temperature ( )
Fig. 36 Maximum standby current (ISB1 and ISB2) vs. Temperature
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OTP ROM
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Fig. 37 Operating voltage under temperature range of 0
to 70
OSC = 4M Hz
OSC =
Max Max Min Min
V
Fig. 38 V-I curve in operating mode, operating frequency is 4M Hz
Fig. 39 V-I curve in operating mode, operating frequency is 32K Hz
This specification is subject to change without prior notice.
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OTP ROM
Appendix
Package Types:
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OTP MCU BJ8P508APJ BJ8P508ANJ BJ8P153APJ BJ8P153SNJ
Package Type PDIP SOP PDIP SOP
Pin Count 8 8 14 14
Package Size 300 mil 150 mil 300 mil 150 mil
This specification is subject to change without prior notice.
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OTP ROM
Package Information
14-Lead Plastic Dual in line (PDIP)
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300 mil
This specification is subject to change without prior notice.
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14-Lead Plastic Small Outline (SOP)
150 mil
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This specification is subject to change without prior notice.
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8-Lead Plastic Dual in line (PDIP) 300 mil
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Symbols A A1 A2 D E E1 L eB
o
Dimension In Inches Min 0.015 0.125 0.367 0.245 0.115 0.335 0
o
Nom 0.130 0.375 0.300 BSC. 0.250 0.130 0.355 7
o
Max 0.210 0.135 0.388 0.255 0.150 0.375 15o
This specification is subject to change without prior notice.
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8-Lead Plastic Small Outline (SOP)
150 mil
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Symbols A A1 B C D E e H L o
Dimension In Inches Min 0.058 0.004 0.013 0.0075 0.168 0.150 0.228 0.015 0o Nom 0.064 0.016 0.008 0.170 0.154 0.050 0.236 0.025 Max 0.068 0.010 0.020 0.0098 0.172 0.157 0.244 0.050 8o
This specification is subject to change without prior notice.
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